In recent years, a variety of device structures are presented, such as a ferroelectric random access memory (FeRAM), a magnetic RAM (MRAM), a phase change RAM (PRAM), or the like, as a next generation nonvolatile RAM (NVRAM) for fast operation possible taking the place of a flash memory. And then a keen development race is performed from points of view of a higher performance, a higher reliability a lower cost and a higher integrity of manufacturing processes. However, each of such the current memory devices has both advantages and disadvantages respectively, and it is still a long way away from realizing an ideal universal memory having every advantage of a static RAM (SRAM), a dynamic RAM (DRAM) and the flash memory.
On the contrary to such the conventional technologies, there is presented a nonvolatile resistive random access memory (RRAM) using a variable resistive element wherein an electrical resistance of the variable resistive element is changed reversibly by applying a voltage pulse thereto. Here, a configuration of such the conventional variable resistive element is shown in FIG. 27.
Such the variable resistive element comprising the conventional configuration includes a structure that a lower electrode 203, a variable resistor body 202 and an upper electrode 201 are layered in order, and has a property that a resistance value is changed reversibly by applying the voltage pulse to between the upper electrode 201 and the lower electrode 203, as shown in FIG. 27. And then it comprises a configuration for being able to realize a novel nonvolatile semiconductor memory device by reading out the resistance value to be changed by such the operation of reversible changing in electrical resistance (referred to as a switching operation hereinafter).
Such the nonvolatile semiconductor memory device is comprised by forming a memory cell array with arranging each of a plurality of memory cells comprising a variable resistive element for each in a row direction and a column direction as a matrix form, and by arranging peripheral circuits to control programming, erasing and reading out operations for each of the memory cell in such the memory cell array. Moreover, for such the memory cell, there is provided such as a memory cell comprised of one selective transistor (T) and one variable resistive element (R) as it is called an 1T/1R type, a memory cell comprised of one variable resistive element (R) as it is called an 1R type, or the like, from a point of view of configuration element difference thereof. Here, a configuration example of the memory cell of 1T/1R type is shown in FIG. 28.
FIG. 28 is an equivalent circuit diagram showing one configuration example of a memory cell array using memory cells of 1T/1R type. In each of the memory cells, a gate electrode of the selective transistor (T) is connected to each of word lines WL1 to WLn respectively, and a source region of the selective transistor (T) is connected to each of source lines SL1 to SLn respectively, as (n) is a natural number. Moreover, one electrode of the variable resistive element (R) in each of the memory cells is connected to a drain region of the selective transistor (T) respectively, and another electrode of the variable resistive element (R) is connected to each of bit lines BL1 to BLm respectively, as (m) is a natural number.
Moreover, each of the word lines WL1 to WLn is connected to a word line decoder 206 respectively, each of the source lines SL1 to SLn is connected to a source line decoder 207 respectively, and each of the bit lines BL1 to BLm is connected to a bit line decoder 205 respectively. Furthermore, there is provided a configuration that a predetermined bit line, word line, or source line is to be selected corresponding to an address input (not shown) for a programming operation, an erasing operation, or a reading out operation respectively, regarding a predetermined memory cell in a memory cell array 204.
FIG. 29 is a cross sectional pattern diagram showing one memory cell comprising the memory cell array 204 as shown in FIG. 28. According to the present configuration, one memory cell is to be comprised of one selective transistor (T) and one variable resistive element (R). Moreover, the selective transistor (T) is comprised of a gate insulating layer 213, a gate electrode 214, a drain diffusion layer region 215 and a source diffusion layer region 216, and then it is formed on a top surface of a semiconductor substrate 211 where an element isolation region 212 is formed. Furthermore, the variable resistive element (R) is comprised of a lower electrode 218, a variable resistor body 219 and an upper electrode 220. According to the present embodiment, the variable resistor body 219 is arranged inside an open part arranged between the lower electrode 218 and the upper electrode 220, however, it may also available that such the elements are arranged in order from the top to be a terraced structure as shown in FIG. 27.
Moreover, the gate electrode 214 in the transistor (T) comprises a word line, and a source line wiring 224 is electrically connected to the source diffusion layer region 216 in the transistor (T) via a contact plug 222. Furthermore, a bit line wiring 223 is electrically connected to the upper electrode 220 in the variable resistive element (R) via a contact plug 221, meanwhile, the lower electrode 218 is electrically connected to the drain diffusion layer region 215 in the transistor (T) via a contact plug 217.
Thus, there is provided a configuration that the transistor becomes to be an on state in the selected memory cell using a change in electric potential of the word line, and it becomes able to program or erase selectively regarding the variable resistive element (R) in the selected memory cell using the change in electric potential of the bit line, by arranging the selective transistor (T) and the variable resistive element (R) as a series connection.
FIG. 30 is an equivalent circuit diagram showing one configuration example of a memory cell array using memory cells of 1R type. Each of the memory cells consists of one variable resistive element (R), wherein one electrode in each of the variable resistive elements (R) is connected to each of word lines WL1 to WLn respectively, and another electrode is connected to each of bit lines BL1 to BLm respectively. Moreover, each of the word lines WL1 to WLn is connected to a word line decoder 233 respectively, and each of the bit lines BL1 to BLm is connected to a bit line decoder 232 respectively. Furthermore, there is provided a configuration that a predetermined bit line or word line is to be selected corresponding to an address input (not shown) for a programming operation, an erasing operation, or a reading out operation respectively, regarding a predetermined memory cell in a memory cell array 231.
FIG. 31 is a diagrammatic perspective view schematically showing one example of a memory cell comprising the memory cell array 231 shown in FIG. 30. As shown in FIG. 31, an upper electrode wiring 243 and a lower electrode wiring 241 are arranged for crossing respectively, and then one of the electrode wirings forms a bit line, and the other forms a word line. Moreover, there is provided a configuration that a variable resistor body 242 is arranged in a region at the intersection of the electrode wirings as it is normally called a cross point. Here, the upper electrode wiring 243 and the resistor body 242 are manufactured in a similar shape according to the example shown in FIG. 31, however, a part electrically contributing to a switching operation in the variable resistor body 242 is to be the region as the cross point at the intersection of the upper electrode wiring 243 and the lower electrode wiring 241.
Regarding a variable resistor body material to be used for the above mentioned variable resistor body 219 shown in FIG. 29 or the variable resistor body 242 shown in FIG. 31, there is disclosed a technology in the following patent document 1 and a nonpatent document 1 by Shangquing Liu, Alex Ignatiev et al., University of Houston, USA, that an electrical resistance is changed reversibly by applying a voltage pulse to a perovskite material known for having a colossal magnetoresistance effect. Such the technology is extremely revolutionary as a change in electrical resistance appears in a wide range of several orders of magnitude even at room temperature without applying a magnetic field, even with using the perovskite material known for having the colossal magnetoresistance effect. Here, a crystalline praseodymium calcium manganese oxide (PCMO: Pr1-xCaxMnO3) layer as a perovskite-type oxide is used as the material for variable resistor body according to the element structure embodied in the patent document 1.
Moreover, according to a nonpatent document 2 and a patent document 2, it is known that an oxide of transition metal elements, such as a titanium oxide (TiO2) layer, a nickel oxide (NiO) layer, a zinc oxide (ZnO) layer, a niobium oxide (Nb2O5) layer, or the like, shows a reversible change in electrical resistance as other materials for variable resistor body. Furthermore, there is reported in detail in a nonpatent document 3 regarding a phenomenon in a switching operation using the NiO layer among such the materials.    Patent document 1: U.S. Pat. No. 6,204,139    Nonpatent document 1: S. Q. Liu et al., “Electric-pulse-induced reversible Resistance change effect in magnetoresistive films”, Applied Physics Letters, vol. 76, pp. 2749-2751 (2000)    Nonpatent document 2: H. Pagnia et al., “Bistable Switching in Electroformed Metal-Insulator-Metal Devices”, Phys. Stat. Sol. (a), vol. 108, pp. 11-65 (1988)    Patent document 2: Japanese published patent publication 2002-537627    Nonpatent document 3: I. G. Baek et al., “Highly Scalable Non-volatile Resistive Memory using Simple Binary Oxide Driven by Asymmetric Unipolar Voltage Pulses”, IEDM 04, pp. 587-590 (2004)